Designing resistor-capacitor networks

3:   Three components

Adding another component to the series or parallel combination discussed in part 2 yields one of four possible networks, which I've labelled (a) - (d) so that we'll all know which one I'm talking about. It's not difficult to find the impedance of each network. The trick is to express it in a way that shows immediately how the network will behave, in terms of up-breaks and down-breaks in the impedance, like this:

As I mentioned in Chapter 2, the up-breaks (where the impedance graph abruptly rotates upwards, or anti-clockwise) happen when a term like [1 + jω/ω₀] appears on the TOP of the impedance expression, and the down-breaks (where the graph starts to head downwards, or rotates clockwise) happen when a similar term appears on the BOTTOM. The break happens at the frequency ω₀.

Two resistors, and one capacitor . . .

Network (a) consists of . . . the new resistor S, in parallel with Z_S (from Chapter 1), or in symbols,

Z_a = S [ 1 + jω/ω₀ ] / [ 1 + jωC (R + S) ] . . . . . where ω₀ = 1/ (CR), as before.

Now, if 1/ (CR) is the break frequency ω₀, then 1/ C(R+S) is evidently another break frequency. It's appeared in network (a), so I'll call it ω_a. So I can write the impedance as

Z_a = S [ 1 + jω/ω₀ ] / [ 1 + jω/ω_a ]

This expression has (1 + jω/ω₀) on the top, and (1 + jω/ω_a) on the bottom, which means that the impedance will begin to rise at ω₀ (an up-break) and at some other frequency ω_a it will begin to fall (a down-break).

Which will happen first? That's easy: {C(R+S)} must be bigger than {CR}, so ω_a must be smaller than ω₀. The down-break will happen at a lower frequency than the up-break. The impedance will be constant at low frequencies, then begin to fall, then level off again.

Network (b) consists of . . . the new resistor S, in series with Z_P (from Chapter 1), or in symbols,

Z_b = (R + S) [ 1 + jωC {RS/(R + S)} ] / [ 1 + jω/ω₀ ] . . . . . where ω₀ = 1/ (CR), as before.

Again, 1/ C {RS/(R+S)} is evidently a break frequency: I'll call this one ω_b. And since {RS/(R+S)} (that is, R in parallel with S) must be smaller than either R or S, then ω_b must be larger than ω₀.

This network has an up-break at ω_b (because the ω_b term is on the top) and a down-break at ω₀ (with the ω₀ term on the bottom), so for this network too, the down-break will happen at a lower frequency than the up-break.

I find it useful to check the algebra with a little common sense, too. Just looking at these two networks, it's clear that at dc (when the capacitor is an open-circuit) they will both look like a resistor, and at the speed of light (when the capacitor is a short-circuit) they will both look like a smaller resistor. The impedance of network (a) will fall from S at dc to [R-in-parallel-with-S] at light-speed. The impedance of network (b) will fall from [R+S] at dc to just S at light-speed. Of course the the down-break will happen at a lower frequency than the up-break.

Straight-line approximations for networks (a) and (b)

Examples: Suppose that R=330Ω and C=470nF, as they were in Chapter 2, making f₀ (= ω₀/2π) = 1.03 kHz, and that S is a 3.3kΩ resistor. What will these two networks do?

In network (a) the new break frequency is ω_a = 1/ C(R+S) = 586 rps, so f_a = 93 Hz. |Z| will be 3300Ω at low frequencies; it will begin to decrease above 93 Hz; and it will level off towards 300Ω at frequencies above 1.03 kHz.

In network (b) the new break frequency is ω_b = 1/ C {RS/(R+S)} = 7090 rps, so f_b = 1.13 kHz. |Z| will be 3.63kΩ at low frequencies; it will begin to decrease above 1.03 kHz; and it will level off towards 3.3kΩ at frequencies above 1.13 kHz. (In other words, the series 3.3kΩ resistor will pretty much swamp everything else).

I have deliberately not shown a scale on the phase graphs, because although the phase moves away from zero between the break frequencies, how far it moves depends on the break frequencies. If they are very far apart, the phase shift will get close to -90°. If they are close together, it may be only a few degrees.

One resistor, and two capacitors . . .

Network (c) consists of . . . the new capacitor D, in parallel with Z_S (from Chapter 1), or in symbols, the impedance is

Z_c = [ 1 + jω/ω₀ ] / jω (C+D) [ 1 + jω {R CD/(C+D)} ]

As before, 1/ R {CD/(C+D)} is evidently a break frequency (because 1/ [Resistance*Capacitance] is ALWAYS a break frequency), and I'll call this one ω_c. Then the impedance can be written more simply as

Z_c = [ 1 + jω/ω₀ ] / jω (C+D) [ 1 + jω/ω_c ] . . . . . where ω₀ = 1/ (CR), as before.

This expression has an up-break at ω₀, and a down-break at ω_c. It also has an over-riding down-slope due to the (jω) term on the bottom, just like a simple series CR network. At dc, the capacitors block any current and the impedance is infinite. The impedance begins to fall as the frequency rises and the capacitors grudgingly allow more and more current to flow through them. And because CD/(C+D) is always smaller than either C or D, it follows that ω_c is always larger than ω₀, so in this network the up-break will happen at a lower frequency than the down-break. If you hadn't noticed, this is the opposite of what happens in networks (a) and (b). So the impedance graph will slope down at low frequencies, then level off, then slope down again.

Network (d) consists of . . . the new capacitor D, in series with Z_P (from Chapter 1), or in symbols, the impedance is

Z_d = [ 1 + jωR (C+D) ] / jωD [ 1 + jω/ω₀ ] . . . . . where ω₀ = 1/ (CR), as before.

This time the up-break happens at the new break frequency of 1/ R(C+D), and I'll call this ω_d, allowing the impedance expression to be written as

Z_d = [ 1 + jω/ω_d ] / jωD [ 1 + jω/ω₀ ]

So this expression has an up-break at ω_d, and a down-break at ω₀. It also has an over-riding down-slope due to the (jω) term on the bottom, just like a simple series CR network, and just like network (c). And since R(C+D) is always larger than RC, ω_d is always smaller than ω₀. The impedance graph will slope down at low frequencies, then level off, then slope down again, just like network (c).

Straight-line approximations for networks (c) and (d)

Examples: Suppose that R=330Ω and C=470nF, as they were in Chapter 2, making f₀ (that is, ω₀/2π) = 1.03 kHz, and that D is a 47nF capacitor. What will these two networks do?

In network (c) the new break frequency is ω_c = 1/ R {CD/(C+D)} = 70.9 krps, so f_c = 11.3 kHz. At low frequencies, |Z| will fall steadily as frequency rises; between 1.03 kHz and 11.3 kHz |Z| will tend to be constant; at higher frequencies |Z| will fall steadily as frequency rises.

In network (d) the new break frequency is ω_d = 1/ R(C+D) = 5.86 krps, so f_d = 933 Hz. At low frequencies, |Z| will fall steadily as frequency rises; between 933 Hz and 1.03 kHz |Z| will tend to be constant; at higher frequencies |Z| will fall steadily as frequency rises. (In other words, it will behave pretty much like a 47nF capacitor!)

For these networks the phase moves away from -90° back towards zero, but again, how far it gets depends on the ratio between the break frequencies. If they are close together, the phase-shift doesn't change much.

The impedance at mid-band - where |Z| is (almost) constant - can be found from the Z equations by assuming a frequency well above the lower break-frequency but much smaller than the upper break-frequency, so that the [ 1 + jω/ω_x ] terms can be approximated (by neglecting one term or the other) to simplify the algebra. (Of course, if the two frequencies are close together, |Z| is never going to be constant, and these |Z| results will be more or less approximate).

For (c), this impedance is: . . . . . . . . . |Z_c| = R [C /(C+D)] . . . . . in the Example, |Z_c| = 300Ω
and for (d), it is: . . . . . . . . . . . . . . . . |Z_d| = R [1 + (C/D)] . . . . . in the Example, |Z_d| = 3.63 kΩ

Designing a real network like (a) or (b)

The equations show how the networks will behave, but designing a real network involves calculating the component values needed to get a particular response shape. The design will specify what the network should do - that is, what its impedance magnitude should be (|Z_L| at low frequencies; |Z_H| at high frequencies), and where its break frequencies (ω_L & ω_H) should be. We need equations that express C, R and S in terms of these four parameters.

Isn't this impossible, though? How can you solve a problem having four specified constraints (the two |Z|'s and the two ω's) with only three variables (C, R and S). Don't three variables allow only three constraints?

The answer is, yes, but the network has only three constraints, because |Z| slopes downwards at 20 dB/decade between the two break frequencies. If (say) |Z_L|, ω_L, and ω_H are fixed, then |Z_H| is also fixed. It depends on |Z_L| and on the ratio between the break frequencies. |Z_H| will be whatever these three parameters force it to be. You can't choose it to be something different. Ye cannot change the laws of physics, as they say on Star Trek. I've ignored |Z_H| in deriving the expressions for C, R & S (below), which may mean that they are not quite in the form you need to solve a particular problem. A little algebra may be necessary before you can apply them. Life's often like that.

Network (a) is designed like this:

Network (b) is designed like this:

Since these two networks do the same job, it's worth asking whether one might be cheaper to build than the other - and it turns out that the capacitor in (a) is always smaller than the one in (b). Smaller often means cheaper, so (a) ought to be the designer's first choice.

A real-life design example

If I was betting real money on the outcome, I would use a simulator to plot the behaviour of BT's model, and then see whether I could get the behaviour of the alternative to be good enough using only preferred-value components.

Designing a real network like (c) or (d)

These networks have three constraints: the two break frequencies, and the mid-band region between them where the impedance - I'll call it |Z_mid| - is reasonably constant.

Network (c) is designed like this:

Network (d) is designed like this:

Looking at these two, it's apparent that the capacitors in (c) are effectively in parallel, whilst those in (d) are effectively in series. One might expect that network (c) would require smaller capacitors, and so be cheaper to make. Let's see.

A design example

... Part 4: Second-order networks ...